Particulars / Model	PCL6046 (Soon on sale)	PCL6045B/PCL6025B	PCL6143/6123/6113	PCD2112	PCD4541/4521/4511/4500	G9103 (Soon on Sale)	G9003
Number of controllabel axes	4	4(PCL6045B) 2(PCL6025B)	4(PCL6143) 2(PCL6123) 1(PCL6113)	1	4(PCD4541) 2(PCD4521) 1(PCD4500/4511)	1	1
Reference clock	19.6608 MHz (Max.30 MHz)	19.6608 MHz (Max. 20 MHz)	19.6608 MHz (Max. 20 MHz)	9.8304 MHz (Max. 20 MHz)	4.9152 MHz (Max. 10 MHz)	80 or 40 MHz	80 or 40 MHz
Maximum output speed *1	6.5 Mpps (Max. 10Mpps)	6.5 Mpps	9.8 Mpps (Max. 15 Mpps)	2.4 Mpps (Max. 5 Mpps)	400 Kpps *2	6.66 Mpps (Max. 10Mpps)	6.66 Mpps
Number of pulse rate setting registers	3 (FL, FH, FA) for correction	3 (FL, FH, FA) for correction	2 (FL, FH)	2 (FL, FH)	2 (FL, FH)	3 (FL, FH, FA) (for correction)	3 (FL, FH, FA) (for correction)
Number of pulse rate setting steps	1 to 65,535(16-bit)	1 to 65,535(16-bit)	1 to 16,383(14-bit)	1 to 8191(13-bit)	1 to 8191(13-bit)	1 to 100,000(17-bit)	1 to 100,000(17-bit)
Pulse rate multiplication setting range	0.1 x to 152.5x	0.1x to 100x	0.3x to 600x	0.5x to 300x	1x to 50x*3	0.1x to 66.6x	0.1x to 66.6x
Acceleration rate setting range	1 to 65,535 (16-bit)	1 to 65,535 (16-bit)	1 to 65,535 (14-bit)	1 to 65,535 (16-bit)	2- to 1023(10-bit) Common to accel/decel	1 to 65535(16-bit)	1 to 65,535(16-bit)
Deceleration rate setting range	1 to 65,535 (16-bit)	1 to 65,535 (16-bit)	1 to 65,535 (14-bit)	1 to 65,535 (16-bit)	2- to 1023(10-bit) Common to accel/decel	1 to 65535(16-bit)	1 to 65,535(16-bit)
Number of positioning pulses setting range	-2,147,483,648 to +2,147,483,647(32-bit)	-2,134,217,728 to +2,134,217,727(28-bit)	-134,217,728 to +134,217,727(28-bit)	0 to 268,435,455(28-bit)	0 to 16,777,215(24-bit) (PCD4511/4421/4541) 1 TO 262,143 (18-bit) (PCD4500)	-134,217,728 to +134,217,727 (28-bit)	-134,217,728 to +134,217,727(28-bit)
CPU interface	8-/16-bit bus	8-/16-bit bus	8-/16-bit bus	Serial bus interface	8-bit bus	interface for communication with G9000	interface for communication with G9000
Ramping-down point setting range	0 to 16,777,215(24-bit)	0 to 16,777,215(24-bit)	0 to 16,777,215(24-bit)	0 to 16,777,215(24-bit)	0 to 65,535(16-bit)	0 to 16,777,215 (24-bit)	0 to 16,777,215 (24-bit)
Package	208-pin BGA	176-pin QFP(PCL6045B) 128-pin QFP(PCL6025B)	176-pin QFP(PCL6143) 128-pin QFP(PCL6123) 80-pin QFP(PCL6113)	18-pin QFP	100-pin QFP(PCD4541) 64-pin QFP(PCD4521) 44-pin QFP(PCD4500/4511)	80-pin QFP	80-pin QFP
External dimension(mm)	12x12	24x24(PCL6045B) 20x14(PCL6025B)	12x12(PCL6113) 20x14(PCL6123) 24x24(PCL6143)	7x7	10x10(PCD4500/4511) 20x14(PCD4521/4541)	12x12	12x12
Supply voltage	+3.3V±10%	+5V±10% and +3.3V±10%	+3.3V±10%	+3.3V±10%	+5V±10% (PCD4511/4521/4541) +5V±5%(PCD4500)	+3.3V±10%	+3.3V±10%

*1 Standard maximum output pulse rate is the available with the reference clock input and the maximum rate in parentheses, with the maximum reference clock input.
*2 For PCD4500 Series, the stated maximum output pulse rate is a practical value and output at higher pulse rate is possible by increasing the multiplication factor.
*3 For PCD4500 Series, thte stated multiplication factors are a practical range and it is possible to set the mulitplication factor at higher than 50x.


Notes on Specification Particulars

Number of controllable axes	Number of axes the single chip can control
Reference clock	Frequency of reference clock which is input to the programmable pulse generator. While a frequency other than the standard one can be input, the resultant output pulse rate may have figures below decimal point.
Maximum output pulse	Maximum rate at which the chip can put put pulses
Number of pulse rate setting registers	There are FL register to which the starting pulse rate is written and FH register to which the operating pulse rate is written. The operating pulse rate can be changed during operation in progress by rewriting it.
Number of pulse rate setting steps	Number of steps available for pulse rate setting. The more the bits, the finer the pulse rate setting is possible
Pulse rate multiplication setting range	Output pulse rate is a product of the value of pulse rate register and that of multiplication factors.
Acceleration rate setting range	Pulse rate slope at acceleration is set. Acceleration time can be calculated from the setting value.
Dceleration rate setting range	Pulse rate slope at deceleration is set. Deceleration time can be calculated from the setting value.
Number of positioning pulses setting range	Number of output pulses for positioning is set.
CPU interface	Typical CPUs are stated un User's Manual.
Ramping-down point setting range	Starting point of deceleration for positioning is set based on the number of remaining pulses.